1. Field of the Invention
The present invention relates to a circuit for generating a wait signal in a semiconductor device, and more particularly to, a circuit for generating a wait signal which can generate the wait signal in every data input or output state of a synchronous pseudo SRAM.
2. Discussion of Related Art
FIG. 1 is a waveform diagram showing a data input or output operation of a general semiconductor device.
Referring to FIG. 1, when a chip select signal /CS is logic low and a clock CLK rises, if an address input enable signal /ADV is logic low, an external address ADD and a write enable signal /WE are inputted. FIG. 1 is a timing diagram when a latency counter is 4. The latency counter defines a clock number for data input or output after an external address is inputted. In FIG. 1, an external address A0 is inputted and a data D0 is written in the fourth clock, and an external address A1 is inputted and a data Q0 is read in the fourth clock.
When a first address input enable signal /ADV is logic low, the address A0 and the write enable signal /WE are inputted, to perform the write operation. Here, a wait signal WAIT is enabled earlier than input time points of data D0, D1, D2 and D3 by one clock. In addition, when the clock CLK rises and the address input enable signal /ADV is logic high, a burst mode is internally executed. The burst mode is maintained by using an address inputted when the address input enable signal /ADV is logic low as a seed address. In the burst mode, the address is internally increased by one by using the seed address as a start address, thereby continuously performing the read or write operation.
When a second address input enable signal /ADV is low, the address A1 and a write enable bar signal become logic high, to perform the read operation. Here, the wait signal WAIT is enabled earlier than output time points of read data Q0, Q1, Q2 and Q3 by one clock.
In general, the wait signal WAIT maintains a high impedance level when the chip select signal /CS is logic high (standby state), is logic low when the chip select signal /CS is logic low, and is high when the clock CLK is inputted and the data is inputted or outputted.
In the conventional arts, a circuit for always generating a wait signal WAIT after three clocks from input of a low address input enable signal /ADV has been employed. However, when the clock CLK rises, if the low address input enable signal /ADV is continuously inputted, the wait signal WAIT maintains logic high after three clocks. That is, when the wait signal WAIT is enabled after three clocks from input of the address input enable signal /ADV, malfunction occurs during the operation.